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GD-240320T28N036A 2.8inch TFT module
Goldconn
9013803010
| Availability: | |
|---|---|
| Interface Description | ||
| PIN NO. | PIN NAME | DESCRIPTION |
| 1 | LEDK | The Anode of LED power |
| 2 | LEDA | The cathode of LED power |
| 3 | NC | NC |
| 4 | VCI | Analog operating voltage. |
| 5 | IOVCC | Logic operating voltage. |
| 6~9 | IM0~IM3 | MPU interface mode select pin,(FYI NOTE1) |
| 10 | GND | Power ground |
| 11 | VSYNC | Frame synchronizing signal for RGB interface operation. |
| 12 | HSYNC | Line synchronizing signal for RGB interface operation. |
| 13 | DOTCLK | Dot clock signal for RGB interface operation. |
| 14 | DE | Data enable signal for RGB interface operation. |
| 15 | GND | Power ground |
| 16-33 | DB0-DB17 | Data bus |
| 34`39 | DB18~DB23 | NC |
| 40 | RESET | Reset pin setting either pin low initializes the LSI Must be reset after power supplied |
| 41 | RD | Read signal input terminal, Active at ‘L’. |
| 42 | CS | Chip select signal input terminal, Active at ‘L’ |
| 43 | /WR | Write enable in MCU parallel interface Display data/command selection pin in 4-line serial interface. - Second Data lane in 2 data lane serial interface. -If not used, please fix this pin at VDDI or DGND. |
| 44 | DCX /SCL | Display data/command selection pin in parallel interface. This pin is used to be serial interface clock DCX=’1’: display data or parameter DCX=’0’: command data. |
| 45 | SDI | When IM [3]: Low, Serial in/out signal. When IM [3]: High, Serial input signal. The data is applied on the rising edge of the SCL signal. |
| 46 | SDO | Serial output signal. |
| The data is applied on the rising edge of the SCL signal. | ||
| 47 | NC | NC. |
| 48 | NC | NC. |
| 49 | NC | NC. |
| 50 | NC | NC. |
| Interface Description | ||
| PIN NO. | PIN NAME | DESCRIPTION |
| 1 | LEDK | The Anode of LED power |
| 2 | LEDA | The cathode of LED power |
| 3 | NC | NC |
| 4 | VCI | Analog operating voltage. |
| 5 | IOVCC | Logic operating voltage. |
| 6~9 | IM0~IM3 | MPU interface mode select pin,(FYI NOTE1) |
| 10 | GND | Power ground |
| 11 | VSYNC | Frame synchronizing signal for RGB interface operation. |
| 12 | HSYNC | Line synchronizing signal for RGB interface operation. |
| 13 | DOTCLK | Dot clock signal for RGB interface operation. |
| 14 | DE | Data enable signal for RGB interface operation. |
| 15 | GND | Power ground |
| 16-33 | DB0-DB17 | Data bus |
| 34`39 | DB18~DB23 | NC |
| 40 | RESET | Reset pin setting either pin low initializes the LSI Must be reset after power supplied |
| 41 | RD | Read signal input terminal, Active at ‘L’. |
| 42 | CS | Chip select signal input terminal, Active at ‘L’ |
| 43 | /WR | Write enable in MCU parallel interface Display data/command selection pin in 4-line serial interface. - Second Data lane in 2 data lane serial interface. -If not used, please fix this pin at VDDI or DGND. |
| 44 | DCX /SCL | Display data/command selection pin in parallel interface. This pin is used to be serial interface clock DCX=’1’: display data or parameter DCX=’0’: command data. |
| 45 | SDI | When IM [3]: Low, Serial in/out signal. When IM [3]: High, Serial input signal. The data is applied on the rising edge of the SCL signal. |
| 46 | SDO | Serial output signal. |
| The data is applied on the rising edge of the SCL signal. | ||
| 47 | NC | NC. |
| 48 | NC | NC. |
| 49 | NC | NC. |
| 50 | NC | NC. |
